Adder-subtractor inputs are 10’s complement signed BCD numbers sign-change algorithm is used whenever subtraction is at hand. In this paper, decimal carry-chain and ripple-carry adders have been implemented on Virtex-4 Xilinx FPGA platforms, for a number of operand sizes comparative performances are presented for binary and BCD digit operands.Īdditionally, three implementations of adders-subtractors have been implemented on FPGA Xilinx Virtex-5 platforms for a number of operand sizes comparative performances are presented for binary and BCD digit operands, respectively. Hardware consumption for BCD will be greater, if coding and decoding processes are not considered as of today, the dramatic decreasing of hardware cost stimulates work on time saving. It will be shown in the practical implementations that adding BCD digits can not only save coding interfaces but moreover provides time delay reductions. Moreover, it has to be pointed out that, within the same range, decimal addition involves shorter carry propagation process than for the straight binary code. Most of them consist in modifying the classical algorithm in such a way as to minimize the computation time of each carry the time complexity may still be proportional to N, but the proportionality constant may be reduced. In order to minimize the computation time, several ideas have been proposed in the literature.
It is well known that in classical algorithms the execution time of any program or circuit is proportional to the number N of digits of the operands.
Signed numbers addition is used as a primitive operation for computing most arithmetic functions, so that it deserves particular attention. Two key ideas have been introduced: (i) the Propagate and generate functions are computed from the input data instead of intermediate BCD sums, and (ii) the functions have been implemented in Xilinx Virtex-4 and Virtex-5 FPGA platforms, taking advantage of the 6-input LUTs structure of Virtex-5 version. This paper resumes some new concepts about carry-chain type algorithms for adding BCD numbers. Issues of hardware realization of decimal arithmetic units appear to be widely open: potential improvements are expected in what refers to algorithm concepts as well as to hardware design. Although other coding systems may be of interest, BCD seems to be the best choice until now. Hardware implementation embedded in recently commercialized general purpose processors is gaining importance.įurthermore, IEEE has recently published a new standard 754-2008 that supports the floating point representation for decimal numbers.Īt the moment, Binary Coded Decimal (BCD) is used for decimal arithmetic algorithm implementations.
Performances required by applications with intensive decimal arithmetic are not met by most of the conventional software-based decimal arithmetic libraries. The reasons come not only from the complexity of coding/decoding interfaces but mostly from the lack of precision and clarity in the results of the binary systems.ĭecimal arithmetic plays a key role in data processing environments such as commercial, financial, and Internet-based applications. In a number of computer arithmetic applications, decimal systems are preferred to the binary ones. Better time delays have been registered for decimal numbers within the same range of operands. Results have been compared to straight implementations of a decimal ripple-carry adder and an FPGA 2's complement binary adder-subtractor using the dedicated carry logic, both carried out on the same platform. All designs are presented with the corresponding time performance and area consumption figures. Carry-chain type circuits have been designed on 4-input LUTs (Virtex-4, Spartan-3) and 6-input LUTs (Virtex-5) Xilinx FPGA platforms. Then, attention is given to FPGA implementations of add/subtract algorithms for 10's complement BCD numbers. Several alternative designs are presented. Some new concepts are presented to compute the P and G functions for carry-chain optimization purposes. This paper first presents a study on the classical BCD adders from which a carry-chain type adder is redesigned to fit within the Xilinx FPGA's platforms.